1. Field of the Invention
The present invention relates to a semiconductor device having a floating gate electrode and a method of manufacturing the same.
2. Description of the Related Art
FIG. 9A is a view showing the structure of conventional nonvolatile memory cells. FIG. 9A is a sectional view in the direction of word lines (channel width direction: a direction perpendicular to a direction in which a channel current flows). A tunnel insulating film 2 is formed on a silicon substrate 1. A plurality of floating gate electrodes 3 are arranged on the tunnel insulating films 2 while being separated from each other by a predetermined distance. An element isolation insulating film 4 is buried between the lower portions of the floating gate electrodes 3. An interelectrode insulating film 5 is formed on part of the side surfaces and the upper surface of each floating gate electrode 3, and the upper surface of the element isolation insulating film 4. A control gate electrode 6 is formed on the interelectrode insulating film 5.
FIG. 9B is a view showing the structure of the nonvolatile memory cells. FIG. 9B is a sectional view in the direction of bit lines (channel length direction: a direction in which a channel current flows). A plurality of cell diffusion layers 7 are formed in the surface of the silicon substrate 1. A plurality of stacking cells CE each including the floating gate electrode 3, interelectrode insulating film 5, and control gate electrode 6 are arranged on the tunnel insulating film 2 between the cell diffusion layer 7 while being separated from each other by a predetermined distance. An interlayer dielectric film 8 is buried between the stacking cells CE.
As shown in FIG. 9B, the floating gate electrodes 3 adjacent in the bit line direction (channel length direction) oppose each other via the interlayer dielectric film 8. Along with advanced micropatterning of memory cells, the opposing distance shortens. Hence, a parasitic capacitance C between the opposing surfaces of the adjacent floating gate electrodes 3 increases. For this reason, the write/erase state of an adjacent cell affects the operation characteristic of a cell of interest, and so-called intercell interference occurs, resulting in an operation error in the memory.
As shown in FIG. 9A, the width of the control gate electrode buried between the floating gate electrodes 3 adjacent in the word line direction (channel width direction) becomes small as micropatterning of memory cells progresses. Consequently, as the buried portion of the control gate electrode is normally made of a semiconductor containing a dopant impurity, the dopant impurity concentration becomes low in the buried portion. Hence, depletion occurs in the buried portion when a high electric field is applied in a write/erase operation. For this reason, the decrease in electric capacitance between the control gate electrode 6 and the floating gate electrode 3 is not negligible, and operation errors in memory cells occur. When depletion occurs in the buried portion, the electric shielding effect between the floating gate electrodes 3 on both sides of the buried portion decreases. For this reason, the probability of occurrence of memory operation errors caused by the intercell interference also becomes high.
Jpn. Pat. Appln. KOKAI Publication No. 8-88285 discloses an EEPROM. In this EEPROM, element formation regions each having a convex shape and a round upper end are formed on a substrate surface while being isolated from each other by isolation trenches. A tunnel film, floating gate electrode, capacitance insulating film, and control gate electrode are formed on the element formation region.
Jpn. Pat. Appln. KOKAI Publication No. 11-177066 discloses an EEPROM manufacturing method. In this method, isolation trenches are formed by self-aligning with floating sate electrodes. After the entire surface is oxidized, the isolation trenches are filled with an insulating film. The surface of the insulating film is removed to expose the side surface of the floating gate electrodes. A second interelectrode insulating film is formed on the entire surface, and control gate electrodes are formed.